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1995 data sheet 8-bit single-chip microcontroller mos integrated circuit description the m pd78p078 is a member of the m pd78078 subseries of the 78k/0 series, in which the on-chip mask rom of the m pd78078 is replaced with a one-time prom or eprom. because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multiple- device production, and early development and time-to-market. the m pd78p078 can be used for evaluation when a system using the m pd78075b subseries is developed. cautions 1. the m pd78075b subseries is different from the m pd78078 subseries in specification. to use the m pd78p078 for evaluation of the m pd78075b subseries, refer to m pd78075b, 78075by subseries user s manual (planned). 2. the m pd78p078kl-t does not maintain planned reliability when used in your systems mass- produced products. please use only experimentally or for evaluation purposes during trial manufacture. the details of functions are described in the users manuals. be sure to read the following manuals before designing. m pd78078, 78078y subseries users manual : u10641e 78k/0 series users manual instructions : u12326e m pd78p078 the mark shows major revised points. the information in this document is subject to change without notice. features pin-compatible with mask rom version (except v pp pin) internal prom: 60 kbytes note 1 ? m pd78p078kl-t: reprogrammable (ideally suited for system evaluation) ? m pd78p078gc, m pd78p078gk: one-time programmable (ideally suited for small-lot production) internal high-speed ram: 1 024 bytes internal expansion ram: 1 024 bytes note 2 internal buffer ram: 32 bytes operable in the same supply voltage as the mask rom version (v dd = 1.8 to 5.5 v) corresponding to qtop tm microcontrollers notes 1. the internal prom capacity can be changed by setting the memory size switching register (ims). 2. the internal expansion ram capacity can be changed by the internal expansion ram size switching register (ixs). remarks 1. refer to 1. differences between m pd78p078 and mask rom versions for the differences between the prom version and the mask rom version. 2. qtop microcontroller is a general term for microcontrollers which incorporate one-time prom and are totally supported by necs programming service (from programming to marking, screening and verification). in this document, the term prom is used in parts common to one-time prom versions and eprom versions. document no. u10168ej3v0ds00 (3rd edition) date published july 1997 n printed in japan
2 m pd78p078 ordering information part number package internal rom quality grade m pd78p078gc-7ea 100-pin plastic qfp (fine pitch) one-time prom standard (14 14 mm, resin thickness: 1.45 mm) m pd78p078gc-8eu 100-pin plastic lqfp (fine pitch) one-time prom standard (14 14 mm, resin thickness: 1.40 mm) m pd78p078gf-3ba 100-pin plastic qfp one-time prom standard (14 20 mm, resin thickness: 2.7 mm) m pd78p078kl-t 100-pin ceramic wqfn eprom not applicable (14 20 mm) caution the m pd78p078gc comes in two types of packages (refer to 11. package drawings). please consult an nec sales representative regarding available packages. please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
3 m pd78p078 78k/0 series development the following shows the 78k/0 series products development. subseries names are shown inside frames. pd78014 pd78002 pd78083 pd78002y 100-pin 100-pin 100-pin 64-pin 64-pin 64-pin 42/44-pin control y subseries products are compatible with i 2 c bus. a timer was added to the pd78054, and the external interface function was enhanced. emi noise reduction version of the pd78078. rom-less versions of the pd78078. an a/d converter and 16-bit timer were added to the pd78002. an a/d converter was added to the pd78002. basic subseries for control. on-chip uart, capable of operating at a low voltage (1.8 v). pd780018 note pd780018y 100-pin serial i/o of the pd78078 was enhanced, and only selected functions are provided. pd78078 pd78070a pd78075b pd78070ay m m mm mm mm m mm m m m m m m inverter control pd780964 64-pin m an a/d converter of the pd780924 was enhanced. pd78078y m m pd78075by pd78018f pd780001 pd78018fy pd78014y 80-pin 80-pin 64-pin 78k/0 series products in mass production products under development emi noise reduction version of the pd78054. uart and d/a converter were added to the pd78014, and i/o was enhanced. low-voltage (1.8 v) operation versions of the pd78014 with several rom and ram capacities available. an a/d converter of the pd780024 was enhanced. emi noise reduction version of the pd78018f. on-chip inverter control circuit and uart, emi noise reduction version. serial i/o of the pd78018f was enhanced, emi noise reduction version. serial i/o of the pd78054 was enhanced, emi noise reduction version. pd780058 80-pin m mm pd780034 pd780024 pd78014h pd780034y pd780024y 64-pin 64-pin 64-pin mm mm m m m m m m m m m fip tm drive pd78044f 100-pin 80-pin 80-pin m m the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 n-ch open-drain input/output was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 m m 100-pin pd780924 64-pin m pd780308 pd78064b pd78064 100-pin 100-pin 100-pin m m sio of the pd78064 was enhanced, and rom and ram were expanded. emi noise reduction version of the pd78064. basic subseries for driving lcds, on-chip uart. m pd780308y m pd78064y m lcd drive m m lv pd78p0914 64-pin m on-chip pwm output, lv digital code decoder, hsync counter. pd78054 m pd78054y m pd78058fy m pd780058y note m pd78058f m pd78044h m m pd780228 pd780208 m m m iebus tm supported pd78098b 80-pin m emi noise reduction version of the pd78098. the iebus controller was added to the pd78054. pd78098 80-pin m m m meter control pd780973 80-pin m general-purpose model of automobile meter driving controller/driver of the pd780805. on-chip automobile meter driving controller/driver. pd780805 100-pin m note under planning
4 m pd78p078 the following table shows the differences among subseries functions. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32 k to 40 k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v available m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780018 48 k to 60 k C 2ch (time-division 3-wire: 1ch) 88 m pd780058 24 k to 60 k 2ch 2ch 3ch (time-division uart: 1ch) 68 1.8 v m pd78058f 48 k to 60 k 3ch (uart: 1ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time-division 3-wire: 1ch) m pd78014h 2ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k C C 1ch 39 C m pd78002 8 k to 16 k 1ch C 53 available m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8 k to 32 k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v available control m pd780924 8ch C fip m pd780208 32 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48 k to 60 k 3ch C C 1ch 72 4.5 v m pd78044h 32 k to 48 k 2ch 1ch 1ch 68 2.7 v m pd78044f 16 k to 40 k 2ch lcd m pd780308 48 k to 60 k 2ch 1ch 1ch 1ch 8ch C C 3ch (time-division uart: 1ch) 57 2.0 v C drive m pd78064b 32 k 2ch (uart: 1ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v available supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C control m pd780805 40 k to 60 k 2ch 8ch 39 2.7 v lv m pd78p0914 32 k 6ch C C 1ch 8ch C C 2ch 54 4.5 v available note 10-bit timer: 1 channel min.
5 m pd78p078 function description item function internal memory ? prom: 60 kbytes note 1 ? ram high-speed ram: 1 024 bytes expansion ram: 1 024 bytes note 2 buffer ram: 32 bytes memory space 64 kbytes general register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time minimum instruction execution time variable function is integrated. when main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0 mhz) clock is selected when subsystem 122 m s (@ 32.768 khz) clock is selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total : 88 ? cmos input : 2 ? cmos input/output : 78 ? n-ch open-drain input/output : 8 a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels serial interface ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable: 1 channel ? 3-wire serial i/o mode (with max. 32-byte on-chip automatic transmit/receive function): 1 channel ? 3-wire serial i/o/uart mode selectable: 1 channel timer ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 4 channels ? watch timer: 1 channel ? watchdog timer: 1 channel timer output 5 pins (14-bit pwm output enable: 1 pin, 8-bit pwm output enable: 2 pins) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, and 5.0 mhz (@ 5.0 mhz with main system clock) 32.768 khz (@ 32.768 khz with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz and 9.8 khz (@ 5.0 mhz with main system clock) notes 1. internal prom capacity can be changed by memory size switching register (ims). 2. internal expansion ram capacity can be changed by internal expansion ram size switching register (ixs).
6 m pd78p078 item function vectored maskable internal: 15, external: 7 interrupt non-maskable internal: 1 source software 1 test input internal: 1, external: 1 supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) ? 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) ? 100-pin plastic qfp (14 20 mm, resin thickness: 2.7 mm) ? 100-pin ceramic wqfn (14 20 mm)
7 m pd78p078 pin configurations (top view) (1) normal operating mode ? 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) m pd78p078gc-7ea ? 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) m pd78p078gc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/r x d p71/so2/t x d p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p84/a4 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p122/rtp2 p121/rtp1 p120/rtp0 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 v dd x1 x2 v pp p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p124/rtp4 p123/rtp3 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p14/ani4 v ss p81/a1 p82/a2 p83/a3 p47/ad7 p46/ad6 p87/a7 p86/a6 p85/a5 p100/ti5/to5 p101/ti6/to6 p37 p90 p91 p92 p93 p94 p95 p96 p103 p102 p01/intp1/ti01 p00/intp0/ti0 0 reset p127/rtp7 p126/rtp6 p125/rtp5 cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss .
8 m pd78p078 ? 100-pin plastic qfp (14 20 mm, resin thickness: 2.7 mm) m pd78p078gf-3ba ? 100-pin ceramic wqfn (14 20 mm) m pd78p078kl-t p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/r x d p71/so2/t x d p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p122/rtp2 p121/rtp1 p120/rtp0 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 v dd x1 x2 v pp p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p124/rtp4 p123/rtp3 v ss p81/a1 p47/ad7 p46/ad6 p87/a7 p86/a6 p85/a5 p100/ti5/to5 p101/ti6/to6 p37 p90 p91 p92 p93 p94 p95 p96 p103 p102 p01/intp1/ti01 p00/intp0/ti00 reset p127/rtp7 p126/rtp6 p125/rtp5 p14/ani4 p15/ani5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 26 27 28 29 30 76 p84/a4 p83/a3 p82/a2 cautions 1. connect v pp pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss .
9 m pd78p078 a0 to a15 : address bus p120 to p127 : port12 ad0 to ad7 : address/data bus p130, p131 : port13 ani0 to ani7 : analog input pcl : programmable clock ano0, ano1 : analog output rd : read strobe asck : asynchronous serial clock reset : reset astb : address strobe rtp0 to rtp7 : real-time output port av dd : analog power supply rxd : receive data av ref0 , av ref1 : analog reference voltage txd : transmit data av ss : analog ground sb0, sb1 : serial bus busy : busy sck0 to sck2 : serial clock buz : buzzer clock si0 to si2 : serial input intp0 to intp6 : interrupt from peripherals so0 to so2 : serial output p00 to p07 : port0 stb : strobe p10 to p17 : port1 ti00, ti01 : timer input p20 to p27 : port2 ti1, ti2, ti5, ti6 : timer input p30 to p37 : port3 to0 to to2, to5, to6 : timer output p40 to p47 : port4 v dd : power supply p50 to p57 : port5 v pp : programming power supply p60 to p67 : port6 v ss : ground p70 to p72 : port7 wait : wait p80 to p87 : port8 wr : write strobe p90 to p96 : port9 x1, x2 : crystal (main system clock) p100 to p103 : port10 xt1, xt2 : crystal (subsystem clock)
10 m pd78p078 (2) prom programming mode ? 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) m pd78p078gc-7ea ? 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) m pd78p078gc-8eu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 reset v ss v dd a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 oe d7 d6 d5 d4 d3 d2 d1 d0 ce v dd (l) open v pp (l) pgm a9 (l) (l) (l) (l) (l) (l) (l) (l) v ss (l) a1 a0 (l) open (l) (l) v ss v dd cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: no connection.
11 m pd78p078 ? 100-pin plastic qfp (14 20 mm, resin thickness: 2.7 mm) m pd78p078gf-3ba ? 100-pin ceramic wqfn (14 20 mm) m pd78p078kl-t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 26 27 28 29 30 76 reset v ss v dd a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 oe d7 d6 d5 d4 d3 d2 d1 d0 v dd (l) open v pp (l) pgm a9 (l) (l) (l) (l) (l) (l) (l) (l) v ss (l) a1 a0 (l) open (l) (l) v ss v dd ce (l) cautions 1. (l): individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset: set to low level. 4. open: no connection. a0 to a16 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program
12 m pd78p078 block diagram to0/p30 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 ano0/p130, ano1/p131 av ss av ref1 intp0/p00 to intp6/p06 si2/rxd/p70 ti00/intp0/p00 so2/txd/p71 sck2/asck/p72 rtp0/p120 to rtp7/p127 ani0/p10 to ani7/p17 av dd av ref0 av ss si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ti5/to5/p100 ti6/to6/p101 buz/p36 pcl/p35 16-bit timer/ event counter 8-bit timer/event counter 1 8-bit timer/event counter 2 8-bit timer/event counter 5 8-bit timer/event counter 6 watchdog timer watch timer serial interface 0 serial interface 2 d/a converter interrupt control buzzer output clock output control a/d converter serial interface 1 p01 to p06 p10 to p17 p20 to p27 p30 to p37 p50 to p57 p60 to p67 p70 to p72 p120 to p127 p130, p131 p40 to p47 p80 to p87 p90 to p96 p100 to p103 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wait/p66 astb/p67 wr/p65 reset x1 x2 xt1/p07 xt2 v dd v ss v pp a0/p80 to a7/p87 port0 port1 port2 port3 port5 port6 port7 external access port8 port9 port4 port12 port13 port10 system control real-time output port ram (2 048 bytes) 78k/0 cpu core prom (60 kbytes) p00 p07
13 m pd78p078 contents 1. differences between m pd78p078 and mask rom versions ..................................... 14 2. pin functions ................................................................................................................ ............... 15 2.1 pins in normal operating mode ............................................................................................... 15 2.2 pins in prom programming mode .......................................................................................... 19 2.3 pin input/output circuits and recommended connection of unused pins ....................... 20 3. memory size switching register (ims) ............................................................................... 24 4. internal expansion ram size switching register (ixs) .............................................. 25 5. prom programming ............................................................................................................. ...... 26 5.1 operating modes ............................................................................................................. .......... 26 5.2 prom write procedure ........................................................................................................ ..... 28 5.3 prom read procedure ......................................................................................................... .... 32 6. program erasure ( m pd78p078kl-t only) ............................................................................ 33 7. opaque film on erasure window ( m pd78p078kl-t only) .............................................. 33 8. one-time prom version screening ...................................................................................... 33 9. electrical specifications .................................................................................................... .34 10. characteristic curves (reference values) .................................................................. 68 11. package drawings ............................................................................................................ ........ 70 12. recommended soldering conditions ................................................................................ 74 appendix a. development tools................................................................................................ 7 6 appendix b. related documents .............................................................................................. 81
14 m pd78p078 notes 1. the internal prom becomes 60 kbytes and the internal high-speed ram becomes 1 024 bytes by the reset input. 2. the internal expansion ram becomes 1 024 bytes by the reset input. caution the prom version and mask rom version differ in noise tolerance and noise emission. when replacing a prom version with a mask rom version when switching from experimental production to mass production, make a thorough evaluation with a cs version (not es version) of the mask rom version. parameter m pd78p078 mask rom versions internal rom type one-time prom/eprom mask rom internal rom capacity 60 kbytes m pd78074b: 32 kbytes m pd78075b: 40 kbytes m pd78076: 48 kbytes m pd78078: 60 kbytes internal expansion ram capacity 1 024 bytes m pd78074b: none m pd78075b: none m pd78076: 1 024 bytes m pd78078: 1 024 bytes internal rom capacity can be changed changeable note 1 not changeable with memory size switching register internal expansion ram capacity can be changeable note 2 not changeable changed with internal expansion ram size switching register ic pin no yes v pp pin yes no on-chip mask option pull-up resistor of yes no p60 to p63 and p90 to p93 pins electrical specifications refer to the data sheet for each version. 1. differences between m pd78p078 and mask rom versions the m pd78p078 is a single-chip microcontroller with an on-chip one-time prom or with an on-chip eprom which has program write, erasure and rewrite capability. it is possible to make all the functions, except for prom specification and mask option of p60 to p63 and p90 to p93 pins, the same as those of the mask rom versions by setting the memory size switching register (ims) and internal expansion ram size switching register (ixs). differences between prom version ( m pd78p078) and mask rom versions ( m pd78074b, 78075b, 78076, 78078) are shown in table 1-1. table 1-1. differences between m pd78p078 and mask rom versions
15 m pd78p078 pin name input/output function after reset alternate function p00 input port 0 input only input intp0/ti00 p01 input/output 8-bit input/output port input/output is specifiable input intp1/ti01 p02 bit-wise. when used as the intp2 p03 input port, it is possible to intp3 p04 connect an on-chip pull-up intp4 p05 resistor by software. intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 input/output port 1 input ani0 to ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. note 2 p20 input/output port 2 input si1 p21 8-bit input/output port so1 p22 input/output is specifiable bit-wise. sck1 p23 when used as the input port, it is possible to connect stb p24 an on-chip pull-up resistor by software. busy p25 si0/sb0 p26 so0/sb1 p27 sck0 p30 input/output port 3 input to0 p31 8-bit input/output port to1 p32 input/output is specifiable bit-wise. to2 p33 when used as the input port, it is possible to connect ti1 p34 an on-chip pull-up resistor by software. ti2 p35 pcl p36 buz p37 2. pin functions 2.1 pins in normal operating mode (1) port pins (1/3) notes 1. when p07/xt1 pins are used as the input ports, set the processor clock control register (pcc) bit 6 (frc) to 1 (be sure not to use the feedback resistor of the subsystem clock oscillator). 2. when p10/ani0 to p17/ani7 pins are used as the analog inputs for the a/d converter, the pull-up resistor is automatically disabled.
16 m pd78p078 pin name input/output function after reset alternate function p40 to p47 input/output port 4 input ad0 to ad7 8-bit input/output port input/output is specifiable in 8-bit units. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. set test input flag (krif) to 1 by falling edge detection. p50 to p57 input/output port 5 input a8 to a15 8-bit input/output port it is possible to directly drive leds. input/output is specifiable bit-wise. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. p60 input/output port 6 n-ch open-drain input/output input p61 8-bit input/output port port. p62 input/output is it is possible to directly p63 specifiable bit-wise. drive leds. p64 when used as the input port, input rd p65 it is possible to connect an wr p66 on-chip pull-up resistor by wait p67 software. astb p70 input/output port 7 input si2/r x d 3-bit input/output port p71 input/output is specifiable bit-wise. so2/t x d when used as the input port, it is possible to connect p72 an on-chip pull-up resistor by software. sck2/asck p80 to p87 input/output port 8 input a0 to a7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. p90 input/output port 9 n-ch open-drain input/output input p91 7-bit input/output port port. p92 input/output is it is possible to directly p93 specifiable bit-wise. drive leds. p94 when used as the input port, p95 it is possible to connect an on-chip p96 pull-up resistor by software. (1) port pins (2/3)
17 m pd78p078 pin name input/output function after reset alternate function p100 input/output port 10 input ti5/to5 4-bit input/output port p101 input/output is specifiable bit-wise. ti6/to6 when used as the input port, it is possible to connect p102, p103 an on-chip pull-up resistor by software. p120 to p127 input/output port 12 input rtp0 to rtp7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. p130, p131 input/output port 13 input ano0, ano1 2-bit input/output port input/output is specifiable bit-wise. when used as the input port, it is possible to connect an on-chip pull-up resistor by software. (1) port pins (3/3)
18 m pd78p078 pin name input/output function after reset alternate function intp0 input external interrupt request input by which the active edge input p00/ti00 intp1 (rising edge, falling edge, or both rising and falling edges) can p01/ti01 intp2 be specified. p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial interface serial data input. input p25/sb0 si1 p20 si2 p70/rxd so0 output serial interface serial data output. input p26/sb1 so1 p21 so2 p71/txd sb0 input/output serial interface serial data input/output. input p25/si0 sb1 p26/so0 sck0 input/output serial interface serial clock input/output. input p27 sck1 p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output. input p23 busy input serial interface automatic transmit/receive busy input. input p24 rxd input asynchronous serial interface serial data input. input p70/si2 txd output asynchronous serial interface serial data output. input p71/so2 asck input asynchronous serial interface serial clock input. input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0). input p00/intp0 ti01 capture trigger signal input to capture register (cr00). p01/intp1 ti1 external count clock input to 8-bit timer (tm1). p33 ti2 external count clock input to 8-bit timer (tm2). p34 ti5 external count clock input to 8-bit timer (tm5). p100/to5 ti6 external count clock input to 8-bit timer (tm6). p101/to6 to0 output 16-bit timer output (tm0) (also used for 14-bit pwm output). input p30 to1 8-bit timer output (tm1). p31 to2 8-bit timer output (tm2). p32 to5 8-bit timer output (tm1) (also used for 8-bit pwm output). p100/ti5 to6 8-bit timer output (tm2) (also used for 8-bit pwm output). p101/ti6 pcl output clock output (for main system clock, subsystem clock input p35 trimming). buz output buzzer output. input p36 rtp0 to rtp7 output real-time output port by which data is output in synchronization input p120 to p127 with a trigger. ad0 to ad7 input/output low-order address/data bus at external memory expansion. input p40 to p47 (2) non-port pins (1/2)
19 m pd78p078 pin name input/output function reset input prom programming mode setting. when +5 v or +12.5 v is applied to the v pp pin and a low level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/verification. a0 to a16 input address bus. d0 to d7 input/output data bus. ce input prom enable input/program pulse input. oe input read strobe input to prom. pgm input program/program inhibit input in prom programming mode. v dd positive power supply. v ss ground potential. pin name input/output function after reset alternate function a0 to a7 output low-order address bus at external memory expansion. input p80 to p87 a8 to a15 output high-order address bus at external memory expansion. input p50 to p57 rd output external memory read operation strobe signal output. input p64 wr external memory write operation strobe signal output. input p65 wait input wait insertion at external memory access. input p66 astb output strobe output which latches the address data output for input p67 ports 4, 5 and 8 to access external memory. ani0 to ani7 input a/d converter analog input. input p10 to p17 ano0, ano1 output d/a converter analog output. input p130, p131 av ref0 input a/d converter reference voltage input. av ref1 input d/a converter reference voltage input. av dd a/d converter analog power supply. connected to v dd . av ss a/d converter ground potential. connected to v ss . reset input system reset input. x1 input main system clock oscillation crystal connection. x2 xt1 input subsystem clock oscillation crystal connection. input p07 xt2 v dd positive power supply. v pp high-voltage applied during program write/verification. connected directly to v ss in normal operating mode. v ss ground potential. (2) non-port pins (2/2) 2.2 pins in prom programming mode
20 m pd78p078 pin name input/output input/output recommended connection for unused pins circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output independently connect to v dd or v ss via a resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e input/output independently connect to v dd via a resistor. p50/a8 to p57/a15 5-a input/output independently connect to v dd or v ss via a resistor. p60 to p63 13-d input/output independently connect to v dd via a resistor. p64/rd 5-a input/output independently connect to v dd or v ss via a resistor. p65/wr p66/wait p67/astb 2.3 pin input/output circuits and recommended connection of unused pins types of input/output circuits of the pins and recommended connection of unused pins are shown in table 2-1. for the configuration of each type of input/output circuit, see figure 2-1. table 2-1. type of input/output circuit of each pin (1/2)
21 m pd78p078 pin name input/output input/output recommended connection for unused pins circuit type p70/si2/rxd 8-a input/output independently connect to v dd or v ss via a resistor. p71/so2/txd 5-a p72/sck2/asck 8-a p80/a0 to p87/a7 5-a p90 to p93 13-d input/output independently connect to v dd via a resistor. p94 to p96 5-a input/output independently connect to v dd or v ss via a resistor. p100/ti5/to5 8-a p101/ti6/to6 p102, p103 5-a p120/rtp0 to p127/rtp7 5-a p130/ano0, p131/ano1 12-a input/output independently connect to v ss via a resistor. reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . v pp connect directly to v ss . table 2-1. type of input/output circuit of each pin (2/2)
22 m pd78p078 figure 2-1. list of pin input/output circuits (1/2) type 2 in type 8-a pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd type 10-a type 11 pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd type 5-a input enable type 5-e pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd schmitt-triggered input with hysteresis characteristics pullup enable data open drain output disable n-ch p-ch v dd v dd p-ch in/out pullup enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator +
23 m pd78p078 figure 2-1. list of pin input/output circuits (2/2) type 12-a type 16 pullup enable data output disable v dd p-ch n-ch p-ch in/out v dd n-ch input enable type 13-d data output disable n-ch in/out v dd rd medium voltage input buffer p-ch analog output voltage xt1 xt2 p-ch feedback cut-off p-ch
24 m pd78p078 selection of internal rom3 rom2 rom1 rom0 rom capacity 1 0 0 0 32 kbytes 1 0 1 0 40 kbytes 1 1 0 0 48 kbytes 1 1 1 0 56 kbytes note 1 1 1 1 60 kbytes other than above setting prohibited ram2 ram1 ram0 selection of internal high-speed ram capacity 1 1 0 1 024 bytes other than above setting prohibited 3. memory size switching register (ims) this is a register to disable use of part of internal memories by software. by setting this memory size switching register (ims), it is possible to get the same memory mapping as that of the mask rom versions with a different internal memory (rom). ims is set with an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 3-1. memory size switching register format ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 7654321 0 symbol ims address r/w fff0h cfh after reset r/w target mask rom versions ims setting value m pd78074b c8h m pd78075b cah m pd78076 cch m pd78078 cfh note when the external device expansion function is used, internal rom capacity should be set to 56 kbytes or less. table 3-1 shows the setting values of ims which make the memory mapping the same as that of the mask rom version. table 3-1. memory size switching register setting values
25 m pd78p078 4. internal expansion ram size switching register (ixs) this register is used to set the internal expansion ram capacity by software. by setting this internal expansion ram size switching register (ixs), it is possible to get the same memory mapping as that of the mask rom versions with a different internal expansion ram. ixs is set with an 8-bit memory manipulation instruction. reset input sets ixs to 0ah. figure 4-1. internal expansion ram size switching register format symbol 7 6 5 4 3 2 1 0 address after reset r/w ixs 0 0 0 0 ixram3 ixram2 ixram1 ixram0 fff4h 0ah w ixram3 ixram2 ixram1 ixram0 selection of internal expansion ram capacity 1 1 0 0 0 bytes 1 0 1 0 1 024 bytes other than above setting prohibited table 4-1 shows the setting values of ixs which make the memory mapping the same as that of the mask rom versions. table 4-1. internal expansion ram size switching register setting values target mask rom versions ixs setting value m pd78074b 0ch note m pd78075b m pd78076 0ah m pd78078 note if a program for the m pd78p078 in which mov ixs, #0ch is written is executed in the m pd78074b and m pd78075b, the operations are not affected.
26 m pd78p078 pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance : l or h 5. prom programming the m pd78p078 has an on-chip 60-kbyte prom as a program memory. for programming, set the prom programming mode with the v pp and reset pins. for the connection of unused pins, refer to pin configura- tions (2) prom programming mode. caution programs must be written in addresses 0000h to efffh (the last address efffh must be specified). they cannot be written by a prom programmer which cannot specify the write address. 5.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 5-1 when the ce, oe and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 5-1. operating modes of prom programming
27 m pd78p078 (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, if oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p078s are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1-ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x times (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin and d0 to d7 pins of multiple m pd78p078s are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
28 m pd78p078 5.2 prom write procedure figure 5-1. page program mode flow chart start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1-ms program pulse verify 4 bytes verify all bytes write end defective product g = start address n = program last address
29 m pd78p078 figure 5-2. page program mode timing a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input
30 m pd78p078 figure 5-3. byte program mode flow chart start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1-ms program pulse verify verify all bytes write end defective product g = start address n = program last address
31 m pd78p078 figure 5-4. byte program mode timing program data input data output program verify a0 to a16 d0 to d7 v pp v pp v dd v dd + 1.5 v dd v ih v il v dd ce v ih v il pgm v ih v il oe cautions 1. v dd should be applied before v pp and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp .
32 m pd78p078 5.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and connect all other unused pins as shown in pin configurations (2) prom programming mode. (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 5-5. figure 5-5. prom read timings a0 to a16 ce (input) oe (input) d0 to d7 hi-z address input data output hi-z
33 m pd78p078 6. program erasure ( m pd78p078kl-t only) the m pd78p078kl-t is capable of erasing (ffh) the data written in a program memory and rewriting. to erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. normally, irradiate ultraviolet rays of 254-nm wavelength. the amount of exposure required to completely erase the programmed data is as follows: ? uv intensity erasing time: 30 w?s/cm 2 or more ? erasure time: 40 min. or more (when a uv lamp of 12 000 m w/cm 2 is used. however, a longer time may be needed because of deterioration in performance of the uv lamp, soiled erasure window, etc.) when erasing the contents of data, set up the uv lamp within 2.5 cm from the erasure window. further, if a filter is provided for a uv lamp, irradiate the ultraviolet rays after removing the filter. 7. opaque film on erasure window ( m pd78p078kl-t only) to protect from unintentional erasure by rays other than that of the lamp for erasing eprom contents, or to protect internal circuit other than eprom from misoperating by rays, cover the erasure window with an opaque film when eprom contents erasure is not performed. 8. one-time prom version screening the one-time prom version ( m pd78p078gc-7ea, 78p078gc-8eu, and 78p078gf-3ba) cannot be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. storage temperature storage time 125 c 24 hours nec offers for an additional fee one-time prom writing to marking, screening, and verify for products designated as qtop microcontroller. please contact an nec sales representative for details.
34 m pd78p078 note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. the parameters apply independently. the device should be operated within the limits specified under dc and ac characteristics. remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. parameter symbol test conditions ratings unit supply voltage v dd C0.3 to +7.0 v v pp C0.3 to +13.5 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to C0.3 to v dd + 0.3 v p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63, p90 to 93 n-ch open-drain C0.3 to +16 v v i3 a9 prom programming mode C0.3 to +13.5 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pins av ss C 0.3 to av ref0 + 0.3 v output current, high i oh per pin C10 ma total for p30 to p37, p56, p57, p60 to p67, C15 ma p90 to p96, p100 to p103, p120 to p127 total for p01 to p06, p10 to p17, p20 to p27, p40 to C15 ma p47, p50 to p55, p70 to p72, p80 to p87, p130, p131 output current, low i ol note per pin peak value 30 ma r.m.s. value 15 ma total for p50 to p55 peak value 100 ma r.m.s. value 70 ma total for p56, p57, p60 to p63 peak value 100 ma r.m.s. value 70 ma total for p30 to p37, p64 to p67, p90 peak value 100 ma to p96, p100 to p103, p120 to p127 r.m.s. value 70 ma total for p20 to p27, p40 to p47, peak value 50 ma p80 to p87 r.m.s. value 20 ma total for p01 to p06, p10 to p17, peak value 50 ma p70 to p72, p130, p131 r.m.s. value 20 ma operating ambient t a C40 to +85 c temperature storage temperature t stg C65 to +150 c 9. electrical specifications absolute maximum ratings (t a = 25 c)
35 m pd78p078 resonator recommended parameter test conditions min. typ. max. unit circuit ceramic oscillation frequency v dd = oscillation voltage 1.0 5.0 mhz resonator (f x ) note 1 range oscillation stabilization after v dd reaches min. value 4ms time note 2 of oscillation voltage range crystal oscillation frequency 1.0 5.0 mhz resonator (f x ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 10 ms time note 2 30 external x1 input frequency 1.0 5.0 mhz clock (f x ) note 1 x1 input high-/low-level 85 500 ns width (t xh , t xl ) parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz, unmeasured pins returned to 0 v. 15 pf i/o capacitance c io f = 1 mhz, p01 to p07, p10 to p17, p20 to 15 pf unmeasured pins p27, p30 to p37, p40 to p47, returned to 0 v. p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 p60 to p63, p90 to p93 20 pf capacitance (t a = 25 c, v dd = v ss = 0 v) remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after a reset or the stop mode has been released. cautions 1. when using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines in the figures as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not connect the ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. v pp c1 x1 c2 x2 v pp c1 x1 c2 x2 x2 x1 pd74hcu04 m
36 m pd78p078 resonator recommended parameter test conditions min. typ. max. unit circuit crystal oscillation frequency 32 32.768 35 khz resonator (f xt ) note 1 oscillation stabilization v dd = 4.5 to 5.5 v 1.2 2 s time note 2 10 external xt1 input frequency 32 100 khz clock (f xt ) note 1 xt1 input high-/low-level 5 15 m s width (t xth , t xtl ) subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. only the oscillator characteristics are shown. for the instruction execution time, refer to ac characteristics. 2. time required for oscillation to stabilize after v dd reaches the minimum value of the oscillation voltage range. cautions 1. when using the oscillation circuit of the subsystem clock, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: ? keep the wiring length as short as possible. ? do not cross the wiring over other signal lines. ? do not route the wiring in the vicinity of lines through which a high fluctuating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . ? do not connect the ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. 2. the amplification factor of the subsystem clock oscillator is designed to be low to reduce the current consumption and therefore, the subsystem clock oscillator is influenced by noise more easily than the main system clock oscillator. when using the subsystem clock, therefore, exercise utmost care in wiring the circuit. v pp c3 xt1 c4 r1 xt2 xt2 xt1 pd74hcu04 m
37 m pd78p078 manufacturer part number frequency recommended circuit constant oscillation voltage range remarks c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) tdk ccr1000k2 1.00 mhz 150 150 0 2.0 5.5 on-chip capacitor ccr2.0mc3 2.00 mhz on-chip on-chip 0 2.0 5.5 on-chip capacitor surface mount type ccr4.0mc3 4.00 mhz on-chip on-chip 0 2.0 5.5 on-chip capacitor surface mount type fcr4.0mc5 4.00 mhz on-chip on-chip 0 2.0 5.5 on-chip capacitor insertion type murata mfg. csb1000j 1.00 mhz 100 100 5.6 1.8 5.5 insertion type co., ltd. csa2.00mg040 2.00 mhz 100 100 0 1.8 5.5 insertion type cst2.00mg040 2.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type csa4.00mg 4.00 mhz 30 30 0 1.8 5.5 insertion type cst4.00mgw 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type csa4.00mgu 4.00 mhz 30 30 0 1.8 5.5 insertion type cst4.00mgwu 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type recommended oscillator constant main system clock: ceramic resonator (t a = C40 to +85 c) main system clock: ceramic resonator (t a = e20 to +80 c) manufacturer part number frequency recommended circuit constant oscillation voltage range remarks c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) kyocera kfr-1000f 1.00 mhz 220 220 0 1.8 5.5 insertion type corporation pbr-1000y 1.00 mhz 220 220 0 1.8 5.5 surface mount type kbr-2.0ms 2.00 mhz 82 82 0 1.8 5.5 insertion type kbr-4.0mkc 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type kbr-4.0msb 4.00 mhz 33 33 0 1.8 5.5 insertion type pbrc4.00b 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor surface mount type pbrc4.00a 4.00 mhz 33 33 0 1.8 5.5 surface mount type caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
38 m pd78p078 parameter symbol test conditions min. typ. max. unit input voltage, high v ih1 p10 to p17, p21, p23, v dd = 2.7 to 5.5 v 0.7 v dd v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, 0.8 v dd v dd v p71, p80 to p87, p94 to p96, p102, p103, p120 to p127, p130, p131 v ih2 p00 to p06, p20, p22, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p24 to p27, p33, p34, p70, p72, p100, 0.85 v dd v dd v p101, reset v ih3 p60 to p63, p90 to v dd = 2.7 to 5.5 v 0.7 v dd 15 v p93 (n-ch open-drain) 0.8 v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v note 0.9 v dd v dd v input voltage, low v il1 p10 to p17, p21, p23, v dd = 2.7 to 5.5 v 0 0.3 v dd v p30 to p32, p35 to p37, p40 to p47, p50 to p57, p64 to p67, 0 0.2 v dd v p71, p80 to p87, p94 to p96, p102, p103, p120 to p127, p130, p131 v il2 p00 to p06, p20, p22, v dd = 2.7 to 5.5 v 0 0.2 v dd v p24 to p27, p33, p34, p70, p72, p100, 0 0.15 v dd v p101, reset v il3 p60 to p63, p90 to p93 4.5 v v dd 5.5 v 0 0.3 v dd v (n-ch open-drain) 2.7 v v dd < 4.5 v 0 0.2 v dd v 0 0.1 v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2 v dd v 2.7 v v dd < 4.5 v 0 0.1 v dd v note 0 0.1 v dd v output voltage, high v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v i oh = C100 m a v dd C 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) note when used as p07, the inverted phase of p07 should be input to xt2 pin using an inverter. remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics.
39 m pd78p078 parameter symbol test conditions min. typ. max. unit output voltage, low v ol1 p50 to p57, p60 to v dd = 4.5 to 5.5 v, 0.4 2.0 v p63, p90 to p93 i ol = 15 ma p01 to p06, p10 to v dd = 4.5 to 5.5 v, 0.4 v p17, p20 to p27, p30 i ol = 1.6 ma to p37, p40 to p47, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2 v dd v open-drain, pulled up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v input leakage current, i lih1 v in = v dd p00 to p06, p10 to p17, 3 m a high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63, p90 to p93 80 m a input leakage current, i lil1 v in = 0 v p00 to p06, p10 to p17, C3 m a low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63, p90 to p93 C3 note m a output leakage current, i loh v out = v dd 3 m a high output leakage current, i lol v out = 0 v C3 m a low dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) note the value is C200 m a (max.) only for 1.5 clock cycles (no wait) when read-out instruction is executed to port 6 (p6), port mode register 6 (pm6), port 9 (p9) and port mode register 9 (pm9). for cases other than the 1.5 clock cycles of read-out instruction execution, the value is C3 m a (max.). remark unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics.
40 m pd78p078 parameter symbol test conditions min. typ. max. unit software pull-up r v in = 0 v, p10 to p17, 4.5 v v dd 5.5 v 15 40 90 k w resistor note 1 p20 to p27, p30 to p37, 2.7 v v dd < 4.5 v 20 500 k w p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 supply current note 2 i dd1 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 6 5.4 16.2 ma lation operating mode v dd = 3.0 v 10% note 7 0.8 2.4 ma (f xx = 2.5 mhz) note 3 v dd = 2.2 v 10% note 7 0.45 1.35 ma 5.0-mhz crystal oscil- v dd = 5.0 v 10% note 6 9.5 28.5 ma lation operating mode v dd = 3.0 v 10% note 7 1.0 3.0 ma (f xx = 5.0 mhz) note 4 i dd2 5.0 mhz crystal oscil- v dd = 5.0 v 10% 1.4 4.2 ma lation halt mode v dd = 3.0 v 10% 0.5 1.5 ma (f xx = 2.5 mhz) note 3 v dd = 2.2 v 10% 280 840 m a 5.0 mhz crystal oscil- v dd = 5.0 v 10% 1.6 4.8 ma lation halt mode v dd = 3.0 v 10% 0.65 1.95 ma (f xx = 5.0 mhz) note 4 i dd3 32.768-khz v dd = 5.0 v 10% 135 270 m a crystal oscillation v dd = 3.0 v 10% 95 190 m a operating mode note 5 v dd = 2.2 v 10% 70 140 m a i dd4 32.768-khz v dd = 5.0 v 10% 25 55 m a crystal oscillation v dd = 3.0 v 10% 5 15 m a halt mode note 5 v dd = 2.2 v 10% 2.5 12.5 m a i dd5 xt1 = v dd v dd = 5.0 v 10% 1 30 m a stop mode v dd = 3.0 v 10% 0.5 10 m a feedback resistor used v dd = 2.2 v 10% 0.3 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10% 0.1 30 m a stop mode v dd = 3.0 v 10% 0.05 10 m a feedback resistor not v dd = 2.2 v 10% 0.05 10 m a used dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. software pull-up resistor can be used only within a range of v dd = 2.7 to 5.5 v. 2. current flowing to v dd pin. however, the current flowing to the a/d converter, d/a converter, and on-chip pull-up resistor is not included. 3. f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h). 4. f xx = f x operation (when osms is set to 01h). 5. when the main system clock is stopped. 6. high-speed mode operation (when processor clock control register (pcc) is set to 00h). 7. low-speed mode operation (when pcc is set to 04h). remarks 1. unless otherwise specified, alternate-function pin characteristics are the same as port pin characteristics. 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency
41 m pd78p078 ac characteristics (1) basic operation (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol test conditions min. typ. max. unit cycle time t cy operating on f xx = f x /2 note 1 v dd = 2.7 to 5.5 v 0.8 64 m s (minimum instruction main system 2.0 64 m s execution time) clock f xx = f x note 2 3.5 v v dd 5.5 v 0.4 32 m s 2.7 v v dd < 3.5 v 0.8 32 m s operating on subsystem clock 40 122 125 m s ti00 input high-/low- t tih00 , 3.5 v v dd 5.5 v 2/f sam + 0.1 note 3 m s level width t til00 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 3 m s 2/f sam + 0.5 note 3 m s ti01 input high-/low- t tih01 ,v dd = 2.7 to 5.5 v 10 m s level width t til01 20 m s ti1, ti2, ti5, ti6 f ti1 v dd = 4.5 to 5.5 v 0 4 mhz input frequency 0 275 khz ti1, ti2, ti5, ti6 input t tih1 ,v dd = 4.5 to 5.5 v 100 ns high-/low-level width t til1 1.8 m s interrupt input high-/ t inth , intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 3 m s low-level width t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 3 m s 2/f sam + 0.5 note 3 m s intp1 to intp6, p40 to p47 v dd = 2.7 to 5.5 v 10 m s 20 m s reset low-level width t rsl v dd = 2.7 to 5.5 v 10 m s 20 m s notes 1. when oscillation mode selection register (osms) is set to 00h. 2. when osms is set to 01h. 3. f sam can be selected as f xx /2 n , f xx /32, f xx /64 or f xx /128 (n = 0 to 4) by bits 0 and 1 (scs0, scs1) of the sampling clock selection register (scs). remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency
42 m pd78p078 t cy vs v dd t cy vs v dd (main system clock f xx = f x /2 operation) (main system clock f xx = f x operation) 60 10 2.0 1.0 0.5 0.4 0 123456 power suppl y volta g e v dd [v] cycle time t cy [ s] m operation guaranteed range 60 10 2.0 1.0 0.5 0.4 0 123456 power suppl y volta g e v dd [v] cycle time t cy [ s] m operation guaranteed range
43 m pd78p078 parameter symbol test conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns address ? data input time t add1 (2.85 + 2n)t cy C 80 ns t add2 (4 + 2n)t cy C 100 ns rd ? data input time t rdd1 (2 + 2n)t cy C 100 ns t rdd2 (2.85 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy C 60 ns t rdl2 (2.85 + 2n)t cy C 60 ns rd ? wait input time t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wr ? wait input time t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy C 100 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.85 + 2n)t cy C 60 ns astb ? rd delay time t astrd 25 ns astb ? wr delay time t astwr 0.85t cy + 20 ns in external fetch rd - ? t rdast 0.85t cy C 10 1.15t cy + 20 ns astb - delay time in external fetch rd - ? t rdadh 0.85t cy C 50 1.15t cy + 50 ns address hold time rd - ? write data output time t rdwd 40 ns wr ? write data output time t wrwd 050ns wr - ? address hold time t wradh 0.85t cy C 20 1.15t cy + 40 ns wait - ? rd - delay time t wtrd 1.15t cy + 40 3.15t cy + 40 ns wait - ? wr - delay time t wtwr 1.15t cy + 30 3.15t cy + 30 ns (2) read/write operation (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 4.5 to 5.5 v) remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
44 m pd78p078 parameter symbol test conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns address ? data input time t add1 (3 + 2n)t cy C 160 ns t add2 (4 + 2n)t cy C 200 ns rd ? data input time t rdd1 (1.4 + 2n)t cy C 70 ns t rdd2 (2.4 + 2n)t cy C 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy C 20 ns t rdl2 (2.4 + 2n)t cy C 20 ns rd ? wait input time t rdwt1 t cy C 100 ns t rdwt2 2t cy C 100 ns wr ? wait input time t wrwt 2t cy C 100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy C 60 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.4 + 2n)t cy C 20 ns astb ? rd delay time t astrd 0.4t cy C 30 ns astb ? wr delay time t astwr 1.4t cy C 30 ns in external fetch rd - ? t rdast t cy C 10 t cy + 20 ns astb - delay time in external fetch rd - ? t rdadh t cy C 80 t cy + 50 ns address hold time rd - ? write data output time t rdwd 0.4t cy C 30 ns wr ? write data output time t wrwd 060ns wr - ? address hold time t wradh t cy C 60 t cy + 60 ns wait - ? rd - delay time t wtrd 0.6t cy + 180 2.6t cy + 180 ns wait - ? wr - delay time t wtwr 0.6t cy + 120 2.6t cy + 120 ns (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) remarks 1. mcs: bit 0 of the oscillation mode selection register (osms) 2. pcc2 to pcc0: bit 2 to bit 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
45 m pd78p078 parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck0 high-/low-level width t kh2 , 4.5 v v dd 5.5 v 400 ns t kl2 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns si0 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time t ksi2 400 ns (from sck0 - ) sck0 ? so0 t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck0 rise, fall time t r2 , when using external device 160 ns t f2 expansion function when not using external device 1 000 ns expansion function parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck0 high-/low-level width t kh1 ,v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns t kl1 t kcy1 /2 C 100 ns si0 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si0 hold time t ksi1 400 ns (from sck0 - ) sck0 ? so0 t kso1 c = 100 pf note 300 ns output delay time (3) serial interface (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0 internal clock output) note c is the so0 output line load capacitance. (ii) 3-wire serial i/o mode (sck0 external clock input) note c is the so0 output line load capacitance.
46 m pd78p078 parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3 200 ns 4 800 ns sck0 high-/low-level width t kh4 , 4.5 v v dd 5.5 v 400 ns t kl4 2.0 v v dd < 4.5 v 1 600 ns 2 400 ns sb0, sb1 setup time t sik4 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso4 r = 1 k w ,v dd = 4.5 to 5.5 v 0 300 ns output delay time c = 100 pf note 0 1 000 ns sck0 - ? sb0, sb1 t ksb t kcy4 ns sb0, sb1 ? sck0 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise, fall time t r4 , when using external device 160 ns t f4 expansion function when not using external device 1 000 ns expansion function (iii) sbi mode (sck0 internal clock output) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3 200 ns 4 800 ns sck0 high-/low-level width t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2 C 50 ns t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso3 r = 1 k w ,v dd = 4.5 to 5.5 v 0 250 ns output delay time c = 100 pf note 0 1 000 ns sck0 - ? sb0, sb1 t ksb t kcy3 ns sb0, sb1 ? sck0 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the sb0, sb1 output line load resistance and load capacitance. (iv) sbi mode (sck0 external clock input) note r and c are the sb0, sb1 output line load resistance and load capacitance.
47 m pd78p078 parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w , 2.7 v v dd 5.5 v 1 600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck0 high-level width t kh5 v dd = 2.7 to 5.5 v t kcy5 /2 C 160 ns t kcy5 /2 C 190 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 300 ns (to sck0 - ) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) sck0 ? sb0, sb1 t kso5 0 300 ns output delay time (v) 2-wire serial i/o mode (sck0 internal clock output) note r and c are the sck0, sb0, sb1 output line load resistance and load capacitance. (vi) 2-wire serial i/o mode (sck0 external clock input) parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 2.7 v v dd 5.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck0 high-level width t kh6 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1 300 ns 2 100 ns sck0 low-level width t kl6 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns sb0, sb1 setup time t sik6 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sck0 ? sb0, sb1 t kso6 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns output delay time c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 800 ns sck0 rise, fall time t r6 , when using external device 160 ns t f6 expansion function when not using external device 1 000 ns expansion function note r and c are the sb0, sb1 output line load resistance and load capacitance.
48 m pd78p078 parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck1 high-/low-level width t kh8 , 4.5 v v dd 5.5 v 400 ns t kl8 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns si1 setup time t sik8 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi8 400 ns (from sck1 - ) sck1 ? so1 t kso8 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck1 rise, fall time t r8 , when using external device 160 ns t f8 expansion function when not using external device 1 000 ns expansion function parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck1 high-/low-level width t kh7 ,v dd = 4.5 to 5.5 v t kcy7 /2 C 50 ns t kl7 t kcy7 /2 C 100 ns si1 setup time t sik7 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi7 400 ns (from sck1 - ) sck1 ? so1 t kso7 c = 100 pf note 300 ns output delay time (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1 internal clock output) note c is the so1 output line load capacitance. (ii) 3-wire serial i/o mode (sck1 external clock input) note c is the so1 output line load capacitance.
49 m pd78p078 parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck1 high-/low-level width t kh9 ,v dd = 4.5 to 5.5 v t kcy9 /2 C 50 ns t kl9 t kcy9 /2 C 100 ns si1 setup time t sik9 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi9 400 ns (from sck1 - ) sck1 ? so1 t kso9 c = 100 pf note 300 ns output delay time sck1 - ? stb - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal t sbw 2.7 v v dd 5.5 v t kcy9 C 30 t kcy9 + 30 ns high-level width 2.0 v v dd < 2.7 v t kcy9 C 60 t kcy9 + 60 ns t kcy9 C 90 t kcy9 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal detection 2.7 v v dd < 4.5 v 150 ns timing) 2.0 v v dd < 2.7 v 200 ns 300 ns busy inactive ? sck1 t sps 2t kcy9 ns (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1 internal clock output) note c is the so1 output line load capacitance.
50 m pd78p078 parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck1 high-/low-level width t kh10 , 4.5 v v dd 5.5 v 400 ns t kl10 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns si1 setup time t sik10 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi10 400 ns (from sck1 - ) sck1 ? so1 t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck1 rise, fall time t r10 , when using external device 160 ns t f10 expansion function when not using external device 1 000 ns expansion function (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1 external clock input) note c is the so1 output line load capacitance.
51 m pd78p078 parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck2 high-/low-level width t kh11 ,v dd = 4.5 to 5.5 v t kcy11 /2 C 50 ns t kl11 t kcy11 /2 C 100 ns si2 setup time t sik11 4.5 v v dd 5.5 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si2 hold time t ksi11 400 ns (from sck2 - ) sck2 ? so2 t kso11 c = 100 pf note 300 ns output delay time (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2 internal clock output) note c is the so2 output line load capacitance. (ii) 3-wire serial i/o mode (sck2 external clock input) parameter symbol test conditions min. typ. max. unit sck2 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns sck2 high-/low-level width t kh12 , 4.5 v v dd 5.5 v 400 ns t kl12 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns si2 setup time t sik12 v dd = 2.0 to 5.5 v 100 ns (to sck2 - ) 150 ns si2 hold time t ksi12 400 ns (from sck2 - ) sck2 ? so2 t kso12 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns output delay time 500 ns sck2 rise, fall time t r12 ,v dd = 4.5 to 5.5 v 1 000 ns t f12 when not using external device expansion function 160 ns note c is the so2 output line load capacitance.
52 m pd78p078 (iii) uart mode (dedicated baud rate generator output) parameter symbol test conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78 125 bps 2.7 v v dd < 4.5 v 39 063 bps 2.0 v v dd < 2.7 v 19 531 bps 9 766 bps (iv) uart mode (external clock input) parameter symbol test conditions min. typ. max. unit asck cycle time t kcy13 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1 600 ns 2.0 v v dd < 2.7 v 3 200 ns 4 800 ns asck high-/low-level width t kh13 , 4.5 v v dd 5.5 v 400 ns t kl13 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1 600 ns 2 400 ns transfer rate 4.5 v v dd 5.5 v 39 063 bps 2.7 v v dd < 4.5 v 19 531 bps 2.0 v v dd < 2.7 v 9 766 bps 6 510 bps asck rise, fall time t r13 ,v dd = 4.5 to 5.5 v 1 000 ns t f13 when not using external device expansion function 160 ns
53 m pd78p078 ac timing test point (excluding x1, xt1 inputs) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points clock timing 1/f x t xl t xh v ih4 (min.) v il4 (max.) x1 input 1/f xt t xtl t xth v ih5 (min.) v il5 (max.) xt1 input ti timing t til00 , t til01 t tih00 , t tih01 ti00, ti01 1/f ti1 t til1 t tih1 ti1, ti2, ti5, ti6
54 m pd78p078 read/write operation external fetch (no wait): t ads t asth t adh t rdd1 hi-z t add1 t astrd t rdl1 t rdh t rdadh t rdast instruction code low-order 8-bit address high-order (low-order) 8-bit address a8 to a15 (a0 to a7) ad0 to ad7 astb rd remark ( ) is effective only in separate bus mode. external fetch (wait insertion): t ads hi-z t add1 t astrd t rdl1 t rdast t wtl t wtrd t rdh t rdadh t adh t asth t rdwt1 t rdd1 instruction code low-order 8-bit address high-order (low-order) 8-bit address wait a8 to a15 (a0 to a7) ad0 to ad7 astb rd remark ( ) is effective only in separate bus mode.
55 m pd78p078 external data access (no wait): hi-z hi-z hi-z t wds t add2 t astrd t rdl2 t wrl t wradh t astwr t rdd2 t ads t asth t adh read data write data t rdh t wdh t wrwd t rdwd low-order 8-bit address high-order (low-order) 8-bit address a8 to a15 (a0 to a7) ad0 to ad7 astb rd wr remark ( ) is effective only in separate bus mode. external data access (wait insertion): hi-z hi-z hi-z t wds t add2 t rdl2 t wrl t astwr t ads t asth t adh read data write data t rdh t wrwd t rdwd t rdd2 t wradh t astrd t wdh t wtl t wtrd t wtl t rdwt2 t wrwt t wtwr low-order 8-bit address high-order (low-order) 8-bit address a8 to a15 (a0 to a7) ad0 to ad7 astb rd wr wait remark ( ) is effective only in separate bus mode.
56 m pd78p078 serial transfer timing 3-wire serial i/o mode: t ksom sck0 to sck2 si0 to si2 so0 to so2 input data output data t kcym t khm t klm t sikm t ksim t rn t fn remark m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12 sbi mode (bus release signal transfer): sck0 t kl3, 4 t kcy3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 sb0, sb1 t kh3, 4 t sbk t sbh t sbl t ksb t r4 t f4 t sbl t sbl sbi mode (command signal transfer): sck0 t kl3, 4 t r4 t f4 t kcy3, 4 t sik3, 4 t ksi3 , 4 t kso3, 4 sb0, sb1 t kh3, 4 t sbk t ksb
57 m pd78p078 2-wire serial i/o mode: sck0 t kl5, 6 t kh5, 6 t kcy5, 6 t ksi5, 6 sb0, sb1 t kso5, 6 t r6 t f6 t sik5, 6 3-wire serial i/o mode with automatic transmit/receive function: t sik9, 10 t kso9, 10 t kh9, 10 t f10 t r10 t kl9, 10 t kcy9, 10 t sbd t sbw so1 si1 sck1 stb d2 d1 d0 d7 d7 d0 d1 d2 t ksi9, 10 3-wire serial i/o mode with automatic transmit/receive function (busy processing): t byh t sps t bys sck1 busy (active high) 789 note 10 note 10 + n note 1 note the signal is not actually low here, but is represented in this way to show the timing.
58 m pd78p078 uart mode (external clock input): asck t kl13 t kh13 t r13 t f13 t kcy13
59 m pd78p078 a/d converter characteristics (t a = e40 to +85 c, av dd = v dd = 2.7 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit total error note 2.7 v av ref0 av dd 1.4 % conversion time t conv 19.1 200 m s sampling time t samp 12/f xx m s analog input voltage v ian av ss av ref0 v reference voltage av ref0 2.7 av dd v av ref0 to av ss resistance r airef0 4k w note excluding quantization error ( 1/2lsb). shown as a percentage of the full scale value. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency d/a converter characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit resolution 8 bit total error r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % settling time c = 30 pf note 1 4.5 v av ref1 5.5 v 10 m s 2.7 v av ref1 < 4.5 v 15 m s 1.8 v av ref1 < 2.7 v 20 m s output resistance r o note 2 10 k w analog reference voltage av ref1 1.8 v dd v av ref1 to av ss resistance r airef1 dacs0, dacs1 = 55h note 2 48 k w notes 1. r and c are the d/a converter output pin load resistance and load capacitance. 2. value for one d/a converter channel. remark dacs0, dacs1: d/a conversion value setting register 0, 1
60 m pd78p078 parameter symbol test conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v data retention supply current i dddr v dddr = 1.8 v 0.1 10 m a when subsystem clock stopped and feedback resistor disconnected release signal setup time t srel 0 m s oscillation stabilization wait t wait release by reset 2 17 /f x ms time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) note 2 12 /f xx or 2 14 /f xx to 2 17 /f xx can be selected by bits 0 to 2 (osts0 to osts2) of oscillation stabilization time selection register. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode released by reset) stop instruction execution v dd v dddr operating mode halt mode stop mode data retention mode t wait reset t srel internal reset operation data retention timing (standby release signal: stop mode released by interrupt signal) stop instruction execution v dd v dddr standby release signal (interrupt request) operating mode halt mode stop mode data retention mode t wait t srel
61 m pd78p078 interrupt input timing intp0 to intp6 t intl t inth reset input timing reset t rsl
62 m pd78p078 prom programming characteristics dc characteristics ( 1) prom write mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh v oh i oh = C1 ma v dd C 1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh1 v oh1 i oh = C1 ma v dd C 1.0 v v oh2 v oh2 i oh = C100 m av dd C 0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C 0.6 v dd v dd + 0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma note corresponding m pd27c1001a symbol.
63 m pd78p078 parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to pgm )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to pgm )t ces t ces 2 m s input data setup time (to pgm )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s input data hold time t dh t dh 2 m s (from pgm - ) oe - ? data output float t df t df 0 250 ns delay time v pp setup time (to pgm )t vps t vps 1.0 ms v dd setup time (to pgm )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? valid data delay time t oe t oe 1 m s oe hold time t oeh 2 m s parameter symbol symbo l note test conditions min. typ. max. unit address setup time (to oe )t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe )t ces t ces 2 m s input data setup time (to oe )t ds t ds 2 m s address hold time (from oe - )t ah t ah 2 m s t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe - )t dh t dh 2 m s oe - ? data output float t df t df 0 250 ns delay time v pp setup time (to oe )t vps t vps 1.0 ms v dd setup time (to oe )t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms oe ? valid data delay time t oe t oe 1 m s oe pulse width during data t lw t lw 1 m s latching pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol.
64 m pd78p078 parameter symbol symbo l note test conditions min. typ. max. unit prom programming mode t sma 10 m s setup time (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) parameter symbol symbo l note test conditions min. typ. max. unit address ? data output t acc t acc ce = oe = v il 800 ns delay time ce ? data output delay time t ce t ce oe = v il 800 ns oe ? data output delay time t oe t oe ce = v il 200 ns oe - ? data output float t df t df ce = v il 060ns delay time address ? data hold time t oh t oh ce = oe = v il 0ns note corresponding m pd27c1001a symbol. (3) prom programming mode (t a = 25 c, v ss = 0 v)
65 m pd78p078 prom write mode timing (page program mode) a2 to a16 a0, a1 d0 to d7 v pp v dd v pp v dd + 1.5 v dd v dd v ih v il ce v ih v il pgm v ih v il oe t lw t pw t ceh t as t ds t vps t vds hi-z hi-z data input t pgms t dh t ahl t ahv t df t oe data output t ah hi-z t ces t oeh t oes page data latch page program program verify
66 m pd78p078 prom write mode timing (byte program mode) a0 to a16 v pp d0 to d7 v pp v dd v dd + 1.5 v dd v dd v ih ce v il v ih pgm v il v ih oe v il t vps t as t ds t vds t ces t pw t oes t oe t oeh t dh hi-z hi-z hi-z t df t ah program verify program data input data output cautions 1. v dd should be applied before v pp , and removed after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected if removal/reinsertion is performed while +12.5 v is being applied to v pp . prom read mode timing a0 to a16 v ih ce v il v ih oe v il d0 to d7 data output effective address hi-z hi-z t ce t acc note 1 t df note 2 t oh t oe note 1 notes 1. if you want to read within the range of t acc , make the oe input delay time from the fall of ce a maximum of t acc C t oe . 2. t df is the time from when either oe or ce first reaches v ih .
67 m pd78p078 prom programming mode setting timing t sma effective address v dd 0 v dd v dd 0 v pp reset a0 to a16
68 m pd78p078 10. characteristic curves (reference values) i dd vs v dd (f x = f xx = 5.0 mhz) supply current i dd [ma] 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 02 34 5 6 78 supply voltage v dd [v] pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h halt (x1 oscillation, xt1 oscillation) pcc = 30h pcc = b0h halt (x1 stop, xt1 oscillation) (t a = 25 c)
69 m pd78p078 i dd vs v dd (f x = 5.0 mhz, f xx = 2.5 mhz) 10.0 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 02345678 pcc = 02h pcc = b0h halt (x1 stop, xt1 oscillation) supply voltage v dd [v] supply current i dd [ma] (t a = 25 c) pcc = 01h pcc = 03h pcc = 04h halt (x1 oscillation, xt1 oscillation) pcc = 30h pcc = 00h
70 m pd78p078 11. package drawings remark the shape and material of es versions are the same as those of mass-produced versions. 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0 0.2 0.630 0.008 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 16.0 0.2 0.630 0.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009 0.002 p100gc-50-7ea-2 k 1.0 0.2 0.039 +0.009 ?.008 l 0.5 0.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125 0.075 0.005 0.003 r s 1.7 max. 5 5 5 5 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51
71 m pd78p078 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00 0.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50 0.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00 0.20 0.551 +0.009 ?.008 a 16.00 0.20 0.630 0.008 g 1.00 0.039 h 0.22 0.009 0.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00 0.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40 0.05 0.055 0.002 r3 3 +7 ? +7 ? d 16.00 0.20 0.630 0.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10 0.05 0.004 0.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b remark the shape and material of es versions are the same as those of mass-produced versions.
72 m pd78p078 remark the shape and material of es versions are the same as those of mass- produced versions. j n m p 80 81 50 100 pin plastic qfp (14 20) 100 1 31 30 51 g detail of lead end s 5 5 c d a b h q k l f m i p100gf-65-3ba1-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.6 0.30 0.10 0.15 20.0 0.2 0.929 0.016 0.031 0.024 0.006 0.026 (t.p.) 0.795 note m n 0.10 0.15 1.8 0.2 0.65 (t.p.) 0.006 0.031 +0.009 ?.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.012 0.551 0.8 0.2 0.071 p 2.7 0.106 0.693 0.016 17.6 0.4 0.8 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 0.004
73 m pd78p078 x100kw-65a-1 item millimeters inches note each lead centerline is located within 0.06 mm (0.003 inch) of its true position (t.p.) at maximum material condition. a b c d e f g h i j k q r s t u w z 20.6 0.4 19.0 13.8 14.6 0.4 1.94 2.14 3.5 max, 0.45 0.10 0.06 0.65 1.0 0.2 c 0.3 0.875 1.125 r 3.17 12.0 0.75 0.2 0.10 0.811 0.016 0.748 0.543 0.575 0.016 0.076 0.084 0.138 max. 0.018 0.003 0.026 0.039 c 0.012 0.034 0.044 r 0.125 0.472 0.030 0.004 +0.004 ?.005 +0.008 ?.009 +0.009 ?.008 a b z m d c e f g w u t k q i j h r 1 100 s 100 pin ceramic wqfn
74 m pd78p078 soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235 ?c, reflow time: 30 seconds or ir35-107-2 less (at 210 ?c or higher), number of reflow processes: 2 or less, exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) vps package peak temperature: 215 ?c, reflow time: 40 seconds or vp15-107-2 less (at 200 ?c or higher), number of reflow processes: 2 or less, exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) partial heating pin temperature: 300 ?c or below, flow time: 3 seconds or less (per pin row) 12. recommended soldering conditions it is recommended that the m pd78p078 be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec sales representative. table 12-1. soldering conditions for surface mount devices (1/2) (1) m pd78p078gc-7ea: 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness: 1.45 mm) note exposure limit before soldering after the dry pack package is opened. storage conditions: 25 ?c and relative humidity at 65% or less. caution do not use different soldering methods together (except for partial heating method).
75 m pd78p078 soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235 ?c, reflow time: 30 seconds or ir35-107-2 less (at 210 ?c or higher), number of reflow processes: 2 or less, exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) vps package peak temperature: 215 ?c, reflow time: 40 seconds or vp15-107-2 less (at 200 ?c or higher), number of reflow processes: 2 or less, exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) wave soldering solder temperature: 260 ?c or below, flow time: 10 seconds or ws60-107-1 less, number of flow processes: 1, preheating temperature: 120 ?c or below (package surface temperature), exposure limit: 7 days note (10 hours pre-baking is required at 125 ?c afterwards) partial heating pin temperature: 300 ?c or below, flow time: 3 seconds or less (per pin row) table 12-1. soldering conditions for surface mount devices (2/2) (2) m pd78p078gc-8eu: 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness: 1.40 mm) soldering method soldering conditions symbol infrared ray reflow package peak temperature: 235 ?c, reflow time: 30 seconds or ir35-00-3 less (at 210 ?c or higher), number of reflow processes: 3 or less vps package peak temperature: 215 ?c, reflow time: 40 seconds or vp15-00-3 less (at 200 ?c or higher), number of reflow processes: 3 or less wave soldering solder temperature: 260 ?c or below, flow time: 10 seconds or ws60-00-1 less, number of flow processes: 1, preheating temperature: 120 ?c or below (package surface temperature) partial heating pin temperature: 300 ?c or below, flow time: 3 seconds or less (per pin row) note exposure limit before soldering after the dry pack package is opened. storage conditions: 25 ?c and relative humidity at 65% or less. (3) m pd78p078gf-3ba: 100-pin plastic qfp (14 20 mm, resin thickness: 2.7 mm) caution do not use different soldering methods together (except for partial heating method).
76 m pd78p078 appendix a. development tools the following development tools are available to support development of systems using the m pd78p078. language processing software ra78k/0 note 1, 2, 3, 4 assembler package common to the 78k/0 series cc78k/0 note 1, 2, 3, 4 c compiler package common to the 78k/0 series df78078 note 1, 2, 3, 4 device file used for the m pd78078 subseries cc78k/0-l note 1, 2, 3, 4 c compiler library source file common to the 78k/0 series prom writing tools pg-1500 prom programmer pa-78p078gc programmer adapter connected to the pg-1500 pa-78p078gf pa-78p078kl-t pg-1500 controller note 1, 2 control program for the pg-1500 debugging tools ie-78000-r in-circuit emulator common to the 78k/0 series ie-78000-r-a in-circuit emulator common to the 78k/0 series (for integrated debugger) ie-78000-r-bk break board common to the 78k/0 series ie-78078-r-em emulation board for evaluation of the m pd78078 subseries ep-78064gc-r emulation probe common to the m pd78064 ep-78064gf-r tgc-100sdw adapter mounted on board of target system created for 100-pin plastic qfp (gc-7ea, gc-8eu type). tgc-100sdw is a product of tokyo eletech corporation (03-5295-1661). contact an nec dealer to purchase this product. ev-9200gf-100 socket mounted on board of target system created for 100-pin plastic qfp (gf-3ba type) sm78k0 note 5, 6, 7 system simulator common to the 78k/0 series id78k0 note 4, 5, 6, 7 integrated debugger for the ie-78000-r-a sd78k/0 note 1, 2 screen debugger for the ie-78000-r df78078 note 1, 2, 4, 5, 6, 7 device file used for the m pd78078 subseries real-time os rx78k/0 note 1, 2, 3, 4 real-time os used for the 78k/0 series mx78k0 note 1, 2, 3, 4 os used for the 78k/0 series notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and compatibles (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux), sparcstation tm (sunos tm ), and ews4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatibles (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based
77 m pd78p078 fuzzy inference development support system fe9000 note 1 /fe9200 note 3 fuzzy knowledge data input tool ft9080 note 1 /ft9085 note 2 translator fi78k0 note 1, 2 fuzzy inference module fd78k0 note 1, 2 fuzzy inference debugger notes 1. pc-9800 series (ms-dos) based 2. ibm pc/at and compatibles (pc dos/ibm dos/ms-dos) based 3. ibm pc/at and compatibles (pc dos/ibm dos/ms-dos + windows) based remarks 1. refer to the 78k/0 series selection guide (u11126e) for information on third party development tools. 2. use the ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 in combination with the df78078.
78 m pd78p078 drawings of conversion socket (ev-9200gf-100) and recommended footprint figure a-1. drawing of ev-9200gf-100 (for reference only) ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f
79 m pd78p078 figure a-2. recommended footprint of ev-9200gf-100 (for reference only) f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p1 item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
80 m pd78p078 drawing of conversion adapter (tgc-100sdw) figure a-3. drawing of tgc-100sdw (for reference only) item millimeters inches b 1.85 0.25 0.073 0.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.125 0.3 0.044 0.012 j 0~5 0.000~0.197 e 3.9 0.154 f 0.25 g 4.5 0.177 tgc-100sdw-g1e 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 item millimeters inches b 0.5x24=12 0.020x0.945=0.472 c 0.5 0.020 a 21.55 0.848 d 0.5x24=12 0.020x0.945=0.472 h 10.9 0.429 i 13.3 0.524 j 15.7 0.618 e 15.0 0.591 f 21.55 g 3.55 0.140 0.848 k 18.1 0.713 l 13.75 0.541 m 0.5x24=12.0 0.020x0.945=0.472 q 10.0 0.394 r 11.3 0.445 s 18.1 0.713 n 1.125 0.3 0.044 0.012 o 1.125 0.2 p 7.5 0.295 0.044 0.008 w 1.8 0.071 x c 2.0 c 0.079 y 0.9 0.035 t 5.0 0.197 u 5.0 v 4- 1.3 4- 0.051 0.197 z 0.3 0.012 f ff f f f f f f f ff h a b c i j k g f e d n o l m x p q r s u protrusion height w v k i m n z j g i h a e d c b y f x t note : product b y tokyo eletech corporation.
81 m pd78p078 appendix b. related documents documents related to devices document name document no. japanese english m pd78078, 78078y subseries users manual u10641j u10641e m pd78076, 78078 data sheet u10167j u10167e m pd78075b, 78075by subseries users manual u12560j planned m pd78074b, 78075b data sheet u12017j u12017e m pd78p078 data sheet u10168j this document 78k/0 series users manualinstructions u12326j u12326e 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd78078 subseries special function register table iem-5607 78k/0 series application notebasic (iii) ieu-767 u10182e documents related to development tools (users manual) (1/2) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly u11789j u11789e language cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming eea-618 eea-1208 know-how cc78k series library source file u12322j pg-1500 prom programmer u11940j eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r eeu-810 u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78078-r-em u10775j u10775e ep-78064 eeu-934 eeu-1469 sm78k0 system simulator windows based reference u10181j u10181e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design.
82 m pd78p078 documents related to development tools (user?s manual) (2/2) document name document no. japanese english sd78k/0 screen debugger introduction eeu-852 u10539e pc-9800 series (ms-dos) based reference u10952j sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference u11279j u11279e documents related to embedded software (users manual) document name document no. japanese english 78k/0 series real-time os basic u11537j installation u11536j 78k/0 series os mx78k0 basic u12257j fuzzy knowledge data input tools eeu-829 eeu-1438 78k/0, 78k/ii, and 87ad series fuzzy inference development support system eeu-862 eeu-1444 translator 78k/0 series fuzzy inference development support system eeu-858 eeu-1441 fuzzy inference module 78k/0 series fuzzy inference development support system eeu-921 eeu-1458 fuzzy inference debugger other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor devices c11893j mei-1202 microcomputer product series guide u11416j caution the contents of the documents listed above are subject to change without prior notice. make sure to use the latest edition when starting design.
83 m pd78p078 [memo]
84 m pd78p078 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
85 m pd78p078 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
2 m pd78p078 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. license not needed : m pd78p078kl-t the customer must judge the need for license : m pd78p078gc-7ea, m pd78p078gc-8eu, m pd78p078gf-3ba no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 fip, iebus, and qtop are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.

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